circuit BubbleFifo : @[:@2.0]
  module FifoRegister : @[:@3.2]
    input clock : Clock @[:@4.4]
    input reset : UInt<1> @[:@5.4]
    input io_enq_write : UInt<1> @[:@6.4]
    output io_enq_full : UInt<1> @[:@6.4]
    input io_enq_din : UInt<8> @[:@6.4]
    input io_deq_read : UInt<1> @[:@6.4]
    output io_deq_empty : UInt<1> @[:@6.4]
    output io_deq_dout : UInt<8> @[:@6.4]
  
    reg stateReg : UInt<1>, clock with :
      reset => (UInt<1>("h0"), stateReg) @[BubbleFifo.scala 51:25:@8.4]
    reg dataReg : UInt<8>, clock with :
      reset => (UInt<1>("h0"), dataReg) @[BubbleFifo.scala 52:24:@9.4]
    node _T_20 = eq(stateReg, UInt<1>("h0")) @[BubbleFifo.scala 54:17:@10.4]
    node _GEN_0 = mux(io_enq_write, UInt<1>("h1"), stateReg) @[BubbleFifo.scala 55:24:@12.6]
    node _GEN_1 = mux(io_enq_write, io_enq_din, dataReg) @[BubbleFifo.scala 55:24:@12.6]
    node _T_21 = eq(stateReg, UInt<1>("h1")) @[BubbleFifo.scala 59:23:@18.6]
    node _GEN_2 = mux(io_deq_read, UInt<1>("h0"), stateReg) @[BubbleFifo.scala 60:23:@20.8]
    node _GEN_3 = mux(io_deq_read, UInt<1>("h0"), dataReg) @[BubbleFifo.scala 60:23:@20.8]
    node _GEN_4 = mux(_T_21, _GEN_2, stateReg) @[BubbleFifo.scala 59:33:@19.6]
    node _GEN_5 = mux(_T_21, _GEN_3, dataReg) @[BubbleFifo.scala 59:33:@19.6]
    node _GEN_6 = mux(_T_20, _GEN_0, _GEN_4) @[BubbleFifo.scala 54:28:@11.4]
    node _GEN_7 = mux(_T_20, _GEN_1, _GEN_5) @[BubbleFifo.scala 54:28:@11.4]
    node _T_23 = eq(stateReg, UInt<1>("h1")) @[BubbleFifo.scala 68:28:@27.4]
    node _T_24 = eq(stateReg, UInt<1>("h0")) @[BubbleFifo.scala 69:29:@29.4]
    io_enq_full <= _T_23 @[BubbleFifo.scala 68:15:@28.4]
    io_deq_empty <= _T_24 @[BubbleFifo.scala 69:16:@30.4]
    io_deq_dout <= dataReg @[BubbleFifo.scala 70:15:@31.4]
    stateReg <= mux(reset, UInt<1>("h0"), _GEN_6) @[BubbleFifo.scala 56:16:@13.8 BubbleFifo.scala 61:16:@21.10]
    dataReg <= mux(reset, UInt<8>("h0"), _GEN_7) @[BubbleFifo.scala 57:15:@14.8 BubbleFifo.scala 62:15:@22.10]

  module BubbleFifo : @[:@123.2]
    input clock : Clock @[:@124.4]
    input reset : UInt<1> @[:@125.4]
    input io_enq_write : UInt<1> @[:@126.4]
    output io_enq_full : UInt<1> @[:@126.4]
    input io_enq_din : UInt<8> @[:@126.4]
    input io_deq_read : UInt<1> @[:@126.4]
    output io_deq_empty : UInt<1> @[:@126.4]
    output io_deq_dout : UInt<8> @[:@126.4]
  
    inst FifoRegister of FifoRegister @[BubbleFifo.scala 81:43:@128.4]
    inst FifoRegister_1 of FifoRegister @[BubbleFifo.scala 81:43:@131.4]
    inst FifoRegister_2 of FifoRegister @[BubbleFifo.scala 81:43:@134.4]
    inst FifoRegister_3 of FifoRegister @[BubbleFifo.scala 81:43:@137.4]
    node _T_17 = not(FifoRegister.io_deq_empty) @[BubbleFifo.scala 84:36:@141.4]
    node _T_18 = not(FifoRegister_1.io_enq_full) @[BubbleFifo.scala 85:31:@143.4]
    node _T_19 = not(FifoRegister_1.io_deq_empty) @[BubbleFifo.scala 84:36:@146.4]
    node _T_20 = not(FifoRegister_2.io_enq_full) @[BubbleFifo.scala 85:31:@148.4]
    node _T_21 = not(FifoRegister_2.io_deq_empty) @[BubbleFifo.scala 84:36:@151.4]
    node _T_22 = not(FifoRegister_3.io_enq_full) @[BubbleFifo.scala 85:31:@153.4]
    io_enq_full <= FifoRegister.io_enq_full @[BubbleFifo.scala 87:10:@156.4]
    io_deq_empty <= FifoRegister_3.io_deq_empty @[BubbleFifo.scala 88:10:@159.4]
    io_deq_dout <= FifoRegister_3.io_deq_dout @[BubbleFifo.scala 88:10:@158.4]
    FifoRegister.clock <= clock @[:@129.4]
    FifoRegister.reset <= reset @[:@130.4]
    FifoRegister.io_enq_write <= io_enq_write @[BubbleFifo.scala 87:10:@157.4]
    FifoRegister.io_enq_din <= io_enq_din @[BubbleFifo.scala 87:10:@155.4]
    FifoRegister.io_deq_read <= _T_18 @[BubbleFifo.scala 85:28:@144.4]
    FifoRegister_1.clock <= clock @[:@132.4]
    FifoRegister_1.reset <= reset @[:@133.4]
    FifoRegister_1.io_enq_write <= _T_17 @[BubbleFifo.scala 84:33:@142.4]
    FifoRegister_1.io_enq_din <= FifoRegister.io_deq_dout @[BubbleFifo.scala 83:31:@140.4]
    FifoRegister_1.io_deq_read <= _T_20 @[BubbleFifo.scala 85:28:@149.4]
    FifoRegister_2.clock <= clock @[:@135.4]
    FifoRegister_2.reset <= reset @[:@136.4]
    FifoRegister_2.io_enq_write <= _T_19 @[BubbleFifo.scala 84:33:@147.4]
    FifoRegister_2.io_enq_din <= FifoRegister_1.io_deq_dout @[BubbleFifo.scala 83:31:@145.4]
    FifoRegister_2.io_deq_read <= _T_22 @[BubbleFifo.scala 85:28:@154.4]
    FifoRegister_3.clock <= clock @[:@138.4]
    FifoRegister_3.reset <= reset @[:@139.4]
    FifoRegister_3.io_enq_write <= _T_21 @[BubbleFifo.scala 84:33:@152.4]
    FifoRegister_3.io_enq_din <= FifoRegister_2.io_deq_dout @[BubbleFifo.scala 83:31:@150.4]
    FifoRegister_3.io_deq_read <= io_deq_read @[BubbleFifo.scala 88:10:@160.4]
